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The present invention relates generally to data encoding and telecommunications and more specifically, to a physical encoding and decoding sub-layer operative to permit the reliable communication of data across a plurality of serial channels.
In recent years there has been an increasing desire to produce electronic products which operate at ever increasing speeds. Of particular note in this regard are telecommunications devices such as routers, bridges and switches. While typical communication line rates for such devices were 10 megabits per second (mbps) for ethernet transmissions less than a decade ago, 100 mbps ethernet line rates have now become commonplace. Moreover, devices are currently being deployed which support 1 gigabit per second (gbps) ethernet line rates.
Data is typically received at an input port of a telecommunications device over a high speed serial communications link. Received data is converted to a parallel word format in accordance with a specified media access control (MAC) for processing within the device. The width of the parallel data output from the MAC protocol is typically specified for the respective MAC protocol. A 10 gb ethernet protocol has been described having a MAC output in the form of a 64 bit wide data words. At such high data rates, the transport of data within the device can be problematic.
While data can be transported through the device as a parallel word to achieve workable clock rates, such is undesirable for a number of reasons. First, wide bus widths consume substantial space on the printed circuit boards for the numerous conductive paths which are required. Second, passing large numbers of conductive signals through backplanes requires large numbers of connector contacts. Often, it is undesirable to provide for the large number of connector contacts that are required to accommodate a 64 bit wide or greater width parallel bus. Additionally, it is recognized that interconnections through backplane connectors contribute to system unreliability and for this reason as well it is preferable to minimize the number of signal paths through backplanes and connectors. Finally, numerous integrated circuits are required in terms of drivers and receivers to interface to wide parallel buses.
In order to minimize the number of printed circuit board runs and backplane connections, parallel data has been segregated into narrower parallel data words and the respective words have been serialized for transmission over a plurality of serial channels. Complex techniques and/or substantial overhead in terms of signal bandwidth and circuitry have typically been necessary to accomplish synchronization and/or framing in such systems.
Moreover, it is desirable to be able for the receive logic to be able to be acquire synchronization of serially transmitted data xe2x80x9cblindxe2x80x9d; i.e. without the use of additional synchronization signal line since the transport of separate synchronization signals also adds to the number of printed circuit board runs and connector contacts that are needed.
It would therefore be desirable to have a data coding, decoding and transport technique which allows the transmission of data reliably through a telecommunications device without employing wide parallel buses and which permits blind acquisition of synchronization at the receiver and reassembly of the transmitted data words.
In accordance with the present invention, a method and apparatus for transporting data over a plurality of serial channels is disclosed. A wide parallel data word is subdivided into a plurality of lesser width parallel data words in which the bits from the wide data word are interleaved across the lesser width data words The lesser width data words are each XORed in parallel with the output of a side scrambler to decorrelate the data transmitted within each channel. The outputs of the side scrambler for each channel comprise cipher data which is decorrelated from the remaining channels to reduce near end crosstalk (NEXT) between channels. The cipher data is applied to a cyclic redundancy code (CRC) encoder which, in the present embodiment, generates two additional bits The two additional bits are derived from the cipher data for the respective channels. The first bit is transmitted in the same channel as the cipher data from which it was derived and is used to verify word alignment at the receive end of the respective serial channel. The second bit is used to assure inter-channel skew. The second bit is rotated across the channel, i.e. transmitted in a channel other than one containing the cipher data from which it was derived. Additionally, control information is encoded on the second bit for each of the respective channels. The control information indicates whether the data word ma) contains an idle signal, (b) contains data valid in the low order bytes, (c) contains data valid in the high order byes, or (d) contains valid data across all of the bytes.
The cipher data plus the two additional bits are serialized for each channel and transmitted serially over a serial link or channel. The serial data transmitted over each channel is then deserialized within receive logic at the receive end of the respective serial channel.
At the receive end of the link, logic is provided to permit the acquisition of word frame alignment, to permit acquisition of inter-channel skew alignment and to obtain the proper seed for use by a descrambler associated with each channel so the cipher data can be converted back into the actual data after synchronization has been achieved. The synchronization process involves a number of steps.
First, word frame alignment is achieved within each channel using the first of the two additional bits transmitted over the serial link. Next, the second bit is employed to achieve inter-channel skew alignment. Once inter-channel skew alignment is achieved, the receiver can identify idle symbols transmitted over the respective link from the control information encoded on the second bits of each channel. The idle information is then XORed with the cipher data to acquire the seed for each of the channels. The parallel cipher data is then XORed in the receiver for each channel with the output of the descrambler for the respective channel using the seed acquired for each channel. The output of the descrambler corresponds to the actual data transmitted over the respective serial links prior the scrambling of such data in the transmitter. Finally, the parallel data output for each channel in the receiver is combined to form the original wide parallel data word.
In a preferred embodiment, a primary pseudo-random sequence generator and a secondary pseudo-random number generator is replicated in each of the scramblers and descramblers. To reduce far end crosstalk (FEXT) between receiver and transmitter signals, the transmission of data in one direction over the plurality of channels proceeds using the primary pseudo-random sequence generators and transmission of data in the opposite direction proceeds using the secondary pseudo-random sequence generators in the transmitter scramblers and the receiver descramblers. The primary and secondary pseudo-random sequence generators are selected so as to decorrelate data transmitted by transmitters in opposite directions over the serial channels.